Modern ASICs such as a system-on-a-chip (SOC) integrate many functions into a single chip. To address the increased complexity in modern designs, the system clock is often split into several local clock domains. By splitting the system clock in this fashion, the loading on the global clock is reduced, which in turn reduces the insertion delay and clock jitter. The local circuits receiving the local clocks thus benefit from reduced uncertainty due to the reduced jitter and are more robust over process and temperature variations.
Although multiple clock domains are thus an attractive alternative as compared to using a single global clock, the local clocks must still be phase aligned with the global clock. A conventional technique to keep multiple clocks in phase alignment involves the use of phase-locked loops (PLLs). But the synchronization from a PLL is typically slow due to their low bandwidth. For example, the lock time for a conventional PLL to align one clock with another is on the order of tens or hundreds of micro seconds. In addition, each additional clock domain requires another PLL such that N clock domains require (N−1) PLLs. The use of such a multiplicity of PLLs as the number N of clock domains is increased requires excessive die area and leads to high power consumption.
Accordingly, there is a need in the art for improved clock synchronization techniques and circuits.